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| MCP3202 2.7V Dual Channel 12-Bit A/D Converter with SPI Serial Interface Features * * * * * * * * * * * 12-bit resolution 1 LSB max DNL 1 LSB max INL (MCP3202-B) 2 LSB max INL (MCP3202-C) Analog inputs programmable as single-ended or pseudo-differential pairs On-chip sample and hold SPI serial interface (modes 0,0 and 1,1) Single supply operation: 2.7V-5.5V 100 ksps max. sampling rate at VDD = 5V 50 ksps max. sampling rate at VDD = 2.7V Low power CMOS technology - 500 nA typical standby current, 5 A max. - 550 A max. active current at 5V Industrial temp range: -40C to +85C 8-pin MSOP, PDIP, SOIC and TSSOP packages Package Types PDIP, MSOP, SOIC, TSSOP CS/SHDN CH0 CH1 VSS 1 2 3 4 8 7 6 5 VDD/VREF CLK DOUT DIN Functional Block Diagram VDD VSS MCP3202 * * CH0 CH1 Input Channel Mux DAC Comparator Applications * * * * Sensor Interface Process Control Data Acquisition Battery Operated Systems Sample and Hold 12-Bit SAR Control Logic Shift Register Description The Microchip Technology Inc. MCP3202 is a successive approximation 12-bit Analog-to-Digital (A/D) Converter with on-board sample and hold circuitry. The MCP3202 is programmable to provide a single pseudodifferential input pair or dual single-ended inputs. Differential Nonlinearity (DNL) is specified at 1 LSB, and Integral Nonlinearity (INL) is offered in 1 LSB (MCP3202-B) and 2 LSB (MCP3202-C) versions. Communication with the device is done using a simple serial interface compatible with the SPI protocol. The device is capable of conversion rates of up to 100 ksps at 5V and 50 ksps at 2.7V. The MCP3202 device operates over a broad voltage range (2.7V-5.5V). Lowcurrent design permits operation with typical standby and active currents of only 500 nA and 375 A, respectively. The MCP3202 is offered in 8-pin MSOP, PDIP, TSSOP and 150 mil SOIC packages. CS/SHDN DIN CLK DOUT (c) 2006 Microchip Technology Inc. DS21034D-page 1 MCP3202 1.0 1.1 ELECTRICAL CHARACTERISTICS Maximum Ratings* PIN FUNCTION TABLE Name VDD/VREF Function +2.7V to 5.5V Power Supply and Reference Voltage Input Channel 0 Analog Input Channel 1 Analog Input Serial Clock Serial Data In Serial Data Out Chip Select/Shutdown Input VDD.........................................................................7.0V All inputs and outputs w.r.t. VSS ...... -0.6V to VDD +0.6V Storage temperature ..........................-65C to +150C Ambient temp. with power applied .....-65C to +125C ESD protection on all pins (HBM)......................... > 4 kV *Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. CH0 CH1 CLK DIN DOUT CS/SHDN ELECTRICAL CHARACTERISTICS All parameters apply at VDD = 5.5V, VSS = 0V, TAMB = -40C to +85C, fSAMPLE = 100 ksps and fCLK = 18*fSAMPLE unless otherwise noted. Parameter Conversion Rate: Conversion Time Analog Input Sample Time Sym tCONV tSAMPLE Min. -- Typ. -- 1.5 Max. 12 Units clock cycles clock cycles ksps ksps bits LSB LSB LSB VDD = VREF = 5V VDD = VREF = 2.7V Conditions Throughput Rate DC Accuracy: Resolution Integral Nonlinearity Differential Nonlinearity fSAMPLE -- -- -- -- 12 0.75 1 0.5 100 50 INL DNL -- -- -- 1 2 1 MCP3202-B MCP3202-C No missing codes over temperature Offset Error -- 1.25 3 LSB Gain Error -- 1.25 5 LSB Dynamic Performance: Total Harmonic Distortion THD -- -82 -- dB VIN = 0.1V to 4.9V@1 kHz Signal to Noise and Distortion SINAD -- 72 -- dB VIN = 0.1V to 4.9V@1 kHz (SINAD) Spurious Free Dynamic Range SFDR -- 86 -- dB VIN = 0.1V to 4.9V@1 kHz Analog Inputs: -- VDD V Input Voltage Range for CH0 or VSS CH1 in Single-Ended Mode See Sections 3.1 and 4.1 Input Voltage Range for IN+ in IN+ IN-- VDD+INPseudo-Differential Mode -- VSS+100 mV See Sections 3.1 and 4.1 Input Voltage Range for IN- in INVSS-100 Pseudo-Differential Mode Leakage Current -- .001 1 A Switch Resistance RSS -- 1k -- See Figure 4-1 Note 1: This parameter is established by characterization and not 100% tested. 2: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 for more information. DS21034D-page 2 (c) 2006 Microchip Technology Inc. MCP3202 ELECTRICAL CHARACTERISTICS (CONTINUED) All parameters apply at VDD = 5.5V, VSS = 0V, TAMB = -40C to +85C, fSAMPLE = 100 ksps and fCLK = 18*fSAMPLE unless otherwise noted. Parameter Sample Capacitor Digital Input/Output: Data Coding Format High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Leakage Current Pin Capacitance (All Inputs/Outputs) Timing Parameters: Clock Frequency Clock High Time Clock Low Time CS Fall To First Rising CLK Edge Data Input Setup Time Data Input Hold Time CLK Fall To Output Data Valid CLK Fall To Output Enable CS Rise To Output Disable CS Disable Time DOUT Rise Time DOUT Fall Time Sym CSAMPLE Min. -- Typ. 20 Max. -- Units pF Conditions See Figure 4-1 VIH VIL VOH VOL ILI ILO CIN, COUT Straight Binary 0.7 VDD -- -- -- -- 0.3 VDD 4.1 -- -- -- -- 0.4 -10 -- 10 -10 -- 10 -- -- 10 V V V V A A pF IOH = -1 mA, VDD = 4.5V IOL = 1 mA, VDD = 4.5V VIN = VSS or VDD VOUT = VSS or VDD VDD = 5.0V (Note 1) TAMB = 25C, f = 1 MHz VDD = 5V (Note 2) VDD = 2.7V (Note 2) fCLK tHI tLO tSUCS tSU tHD tDO tEN tDIS tCSH tR tF -- 250 250 100 -- -- -- -- -- 500 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.8 0.9 -- -- -- 50 50 200 200 100 -- 100 100 MHz MHz ns ns ns ns ns ns ns ns ns ns ns See Test Circuits, Figure 1-2 See Test Circuits, Figure 1-2 See Test Circuits, Figure 1-2 Note 1 See Test Circuits, Figure 1-2 Note 1 See Test Circuits, Figure 1-2 Note 1 Power Requirements: 2.7 -- 5.5 V Operating Voltage VDD Operating Current IDD -- 375 550 A VDD = 5.0V, DOUT unloaded -- 0.5 5 A CS = VDD = 5.0V Standby Current IDDS Temperature Ranges: Specified Temperature Range TA -40 -- +85 C -40 -- +85 C Operating Temperature Range TA Storage Temperature Range TA -65 -- +150 C Thermal Package Resistance: Thermal Resistance, 8L-PDIP JA -- 85 -- C/W Thermal Resistance, 8L-SOIC JA -- 163 -- C/W Thermal Resistance, 8L-MSOP JA -- 206 -- C/W JA -- -- C/W Thermal Resistance, 8L-TSSOP Note 1: This parameter is established by characterization and not 100% tested. 2: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 for more information. (c) 2006 Microchip Technology Inc. DS21034D-page 3 MCP3202 tCSH CS tSUCS tHI CLK tSU DIN tHD tLO MSB IN tEN tDO NULL BIT MSB OUT tR tF LSB tDIS DOUT FIGURE 1-1: Serial Timing. Load circuit for tDIS and tEN Test Point VDD 3 k Test Point DOUT CL = 100 pF 100 pF VSS 3 k VDD/2 tDIS Waveform 2 tEN Waveform tDIS Waveform 1 Load circuit for tR, tF, tDO 1.4V DOUT Voltage Waveforms for tR, tF DOUT tR tF CLK DOUT VOH VOL Voltage Waveforms for tEN CS 1 2 3 4 B11 tEN Voltage Waveforms for tDO CLK tDO DOUT Voltage Waveforms for tDIS CS DOUT Waveform 1* TDIS DOUT Waveform 2 10% VIH 90% * Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control. FIGURE 1-2: Test Circuits. DS21034D-page 4 (c) 2006 Microchip Technology Inc. MCP3202 2.0 Note: TYPICAL PERFORMANCE CHARACTERISTICS The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE,TA = 25C 1.0 0.8 0.6 0.4 Positive INL 2.0 1.5 1.0 VDD = 2.7V Positive INL 0.5 0.0 -0.5 Negative INL -1.0 -1.5 -2.0 0 20 40 60 80 100 INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 25 50 75 100 125 150 Negative INL Sample Rate (ksps) INL (LSB) Sample Rate (ksps) FIGURE 2-1: Rate. Integral Nonlinearity (INL) vs. Sample FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V). 1.0 0.8 0.6 0.4 Positive INL FSAMPLE = 100 ksps 1.0 0.8 0.6 0.4 Positive INL FSAMPLE = 50 ksps INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 3.0 3.5 4.0 4.5 5.0 Negative INL INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 2.5 3.0 3.5 4.0 4.5 5.0 Negative INL VDD(V) VDD(V) FIGURE 2-2: Integral Nonlinearity (INL) vs. VDD. FIGURE 2-5: Integral Nonlinearity (INL) vs. VDD. 1.0 0.8 0.6 0.4 1.0 0.8 0.6 0.4 VDD = 2.7V FSAMPLE = 50 ksps INL (LSB) INL (LSB) 0 512 1024 1536 2048 2560 3072 3584 4096 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Code Digital Code FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part). FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V). (c) 2006 Microchip Technology Inc. DS21034D-page 5 MCP3202 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE,TA = 25C 1.0 0.8 0.6 0.4 Positive INL 1.0 0.8 0.6 0.4 VDD = 2.7V FSAMPLE = 50 ksps Positive INL INL (LSB) INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100 Negative INL 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100 Negative INL Temperature (C) Temperature (C) FIGURE 2-7: Temperature. Integral Nonlinearity (INL) vs. FIGURE 2-10: Integral Nonlinearity Temperature (VDD = 2.7V). (INL) vs. 1.0 0.8 0.6 0.4 2.0 1.5 1.0 Positive DNL V DD = 2.7V DNL (LSB) DNL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 25 50 75 100 125 150 Negative DNL 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 20 Positive DNL Negative DNL 40 60 80 100 Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-8: Differential Sample Rate. Nonlinearity (DNL) vs. FIGURE 2-11: Differential Sample Rate (VDD = 2.7V). Nonlinearity (DNL) vs. 1.0 0.8 0.6 Positive DNL 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 3.0 3.5 4.0 4.5 5.0 Negative DNL FSAMPLE = 100 ksps 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 2.5 3.0 3.5 4.0 4.5 5.0 Negative DNL Positive DNL FSAMPLE = 50 ksps DNL (LSB) DNL (LSB) VDD(V) VDD(V) FIGURE 2-9: Differential Nonlinearity (DNL) vs. VDD. FIGURE 2-12: Differential Nonlinearity (DNL) vs. VDD. DS21034D-page 6 (c) 2006 Microchip Technology Inc. MCP3202 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE,TA = 25C 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 V DD = 2.7V FSAMPLE = 50 ksps DNL (LSB) Digital Code DNL (LSB) Digital Code FIGURE 2-13: Differential Nonlinearity Code (Representative Part). (DNL) vs. FIGURE 2-16: Differential Nonlinearity Code (Representative Part, VDD = 2.7V). (DNL) vs. 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100 Negative DNL Positive DNL 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100 Negative DNL V DD = 2.7V FSAMPLE = 50 ksps Positive DNL DNL (LSB) Temperature (C) DNL (LSB) Temperature (C) FIGURE 2-14: Differential Temperature. Nonlinearity (DNL) vs. FIGURE 2-17: Differential Temperature (VDD = 2.7V). Nonlinearity (DNL) vs. 2.0 1.5 FSAMPLE = 10 ksps 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.5 3.0 3.5 4.0 4.5 5.0 Offset Error (LSB) Gain Error (LSB) 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 FSAMPLE = 100 ksps FSAMPLE = 50 ksps FSAMPLE = 100 ksps FSAMPLE = 50 ksps FSAMPLE = 10 ksps 2.5 3.0 3.5 4.0 4.5 5.0 VDD(V) VDD(V) FIGURE 2-15: Gain Error vs. VDD. FIGURE 2-18: Offset Error vs. VDD. (c) 2006 Microchip Technology Inc. DS21034D-page 7 MCP3202 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE,TA = 25C 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 V DD = 5V FSAMPLE = 100 ksps 50 75 100 V DD = 2.7V FSAMPLE = 50 ksps 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100 VDD = 2.7V FSAMPLE = 50 ksps VDD = 5V FSAMPLE = 100 ksps Offset Error (LSB) Gain Error (LSB) Temperature (C) Temperature (C) FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-22: Offset Error vs. Temperature. 100 90 80 70 VDD = 5V FSAMPLE = 100 ksps 100 90 80 70 60 50 40 30 20 10 0 VDD = 2.7V FSAMPLE = 50 ksps VDD = 5V FSAMPLE = 100 ksps 60 50 40 30 20 10 0 1 VDD = 2.7V FSAMPLE = 50 ksps 10 100 SINAD (dB) SNR (dB) 1 10 100 Input Frequency (kHz) Input Frequency (kHz) FIGURE 2-20: Signal to Noise Ratio (SNR) vs. Input Frequency. FIGURE 2-23: Signal to Noise and Distortion (SINAD) vs. Input Frequency. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1 10 100 VDD = 5V FSAMPLE = 100 ksps VDD = 2.7V FSAMPLE = 50 ksps 80 70 60 VDD = 5V FSAMPLE = 100 ksps SINAD (dB) THD (dB) 50 40 30 20 10 0 -40 -35 -30 -25 -20 -15 VDD = 2.7V FSAMPLE = 50 ksps -10 -5 0 Input Frequency (kHz) Input Signal Level (dB) FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency. FIGURE 2-24: Signal to Noise and Distortion (SINAD) vs. Signal Level. DS21034D-page 8 (c) 2006 Microchip Technology Inc. MCP3202 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE,TA = 25C 12.0 12.0 FSAMPLE = 50ksps 11.5 VDD = 5V FSAMPLE = 100 ksps 11.5 11.0 ENOB (rms) 11.0 10.5 10.0 9.5 FSAMPLE = 100 ksps ENOB (rms) 10.5 10.0 9.5 9.0 8.5 V DD = 2.7V FSAMPLE = 50 ksps 1 10 100 9.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 8.0 VDD (V) Input Frequency (kHz) FIGURE 2-25: Effective Number of Bits (ENOB) vs. VDD. FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency. 100 90 80 70 60 50 40 30 20 10 0 1 10 100 V DD = 2.7V FSAMPLE = 50 ksps 0 Power Supply Rejection (dB) VDD = 5V FSAMPLE = 100 ksps -10 -20 -30 -40 -50 -60 -70 -80 1 10 100 1000 10000 SFDR (dB) Input Frequency (kHz) Ripple Frequency (kHz) FIGURE 2-26: Spurious Free (SFDR) vs. Input Frequency. Dynamic Range FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10000 20000 VDD = 5V FSAMPLE = 100 ksps Amplitude (dB) 30000 40000 50000 Amplitude (dB) FINPUT = 9.985 kHz 4096 points 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5000 10000 VDD = 2.7V FSAMPLE = 50 ksps FINPUT = 998.76 Hz 4096 points 15000 20000 25000 Frequency (Hz) Frequency (Hz) FIGURE 2-27: Frequency Spectrum of 10 kHz input (Representative Part). FIGURE 2-30: Frequency Spectrum of 1 kHz input (Representative Part, VDD = 2.7V). (c) 2006 Microchip Technology Inc. DS21034D-page 9 MCP3202 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE,TA = 25C 500 450 400 350 All points at FCLK = 1.8 MHz except at VDD = 2.5V, FCLK = 900 kHz 80 70 60 CS = V DD IDD (A) 300 250 200 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 IDDS (pA) 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 2-31: IDD vs. VDD. FIGURE 2-34: IDDS vs. VDD. 500 450 400 350 V DD = 5V 100.00 VDD = CS = 5V 10.00 IDD (A) 250 200 150 100 50 0 10 100 1000 10000 V DD = 2.7V IDDS (nA) 300 1.00 0.10 0.01 -50 -25 0 25 50 75 100 Clock Frequency (kHz) Temperature (C) FIGURE 2-32: IDD vs. Clock Frequency. FIGURE 2-35: IDDS vs. Temperature. 500 2.0 Analog Input Leakage (nA) 450 400 350 V DD = 5V FCLK = 1.8 MHz 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100 VDD = 5V FCLK = 1.8 MHz IDD (A) 300 250 200 150 100 50 0 -50 -25 0 25 50 75 100 VDD = 2.7V FCLK = 900 kHz Temperature (C) Temperature (C) FIGURE 2-33: IDD vs. Temperature. FIGURE 2-36: Analog Input leakage current vs. Temperature. DS21034D-page 10 (c) 2006 Microchip Technology Inc. MCP3202 3.0 3.1 PIN DESCRIPTIONS CH0/CH1 4.1 Analog Inputs Analog inputs for channels 0 and 1 respectively. These channels can programmed to be used as two independent channels in single ended-mode or as a single pseudo-differential input where one channel is IN+ and one channel is IN-. See Section 5.0 for information on programming the channel configuration. 3.2 Chip Select/Shutdown (CS/SHDN) The CS/SHDN pin is used to initiate communication with the device when pulled low and will end a conversion and put the device in low power standby when pulled high. The CS/SHDN pin must be pulled high between conversions. The MCP3202 device offers the choice of using the analog input channels configured as two single-ended inputs or a single pseudo-differential input. Configuration is done as part of the serial command before each conversion begins. When used in the pseudo-differential mode, CH0 and CH1 are programmed as the IN+ and IN- inputs as part of the command string transmitted to the device. The IN+ input can range from IN- to VREF (VDD + IN-). The IN- input is limited to 100 mV from the VSS rail. The IN- input can be used to cancel small signal common-mode noise which is present on both the IN+ and IN- inputs. For the A/D Converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 12-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. In this diagram, it is shown that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor, CSAMPLE. Consequently, larger source impedances increase the offset, gain, and integral linearity errors of the conversion. Ideally, the impedance of the signal source should be near zero. This is achievable with an operational amplifier such as the MCP601 which has a closed loop output impedance of tens of ohms. The adverse affects of higher source impedances are shown in Figure 4-2. When operating in the pseudo-differential mode, if the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[VDD + (IN-)] - 1 LSB}, then the output code will be FFFh. If the voltage level at IN- is more than 1 LSB below VSS, then the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above VSS, then the FFFh code will not be seen unless the IN+ input level goes above VDD level. 3.3 Serial Clock (CLK) The SPI clock pin is used to initiate a conversion and to clock out each bit of the conversion as it takes place. See Section 6.2 for constraints on clock speed. 3.4 Serial Data Input (DIN) The SPI port serial data input pin is used to clock in input channel configuration data. 3.5 Serial Data Output (DOUT) The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place. 4.0 DEVICE OPERATION The MCP3202 A/D Converter employs a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the second rising edge of the serial clock after the start bit has been received. Following this sample time, the input switch of the converter opens and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 12-bit digital output code. Conversion rates of 100 ksps are possible on the MCP3202. See Section 6.2 for information on minimum clock rates. Communication with the device is done using a 3-wire SPI-compatible interface. 4.2 Digital Output Code The digital output code produced by an A/D Converter is a function of the input signal and the reference voltage. For the MCP3202, VDD is used as the reference voltage. As the VDD level is reduced, the LSB size is reduced accordingly. The theoretical digital output code produced by the A/D Converter is shown below. 4096*V IN Digital Output Code = -----------------------V DD where: VIN = analog input voltage VDD = supply voltage (c) 2006 Microchip Technology Inc. DS21034D-page 11 MCP3202 VDD VT = 0.6V Sampling Switch SS RS = 1 k CSAMPLE = DAC capacitance = 20 pF VSS Legend VA RSS CHx CPIN VT ILEAKAGE SS RS CSAMPLE RSS CHx VA CPIN 7 pF VT = 0.6V ILEAKAGE 1 nA = = = = = = = = = signal source source impedance input channel pad input pin capacitance threshold voltage leakage current at the pin due to various junctions sampling switch sampling switch resistor sample/hold capacitance FIGURE 4-1: Analog Input Model. 2.0 Clock Frequency (MHz) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 100 1000 V DD = 2.7V VDD = 5V 10000 Input Resistance (Ohms) FIGURE 4-2: Maximum Clock Frequency vs. Input Resistance (RS) to maintain less than a 0.1 LSB deviation in INL from nominal conditions. DS21034D-page 12 (c) 2006 Microchip Technology Inc. MCP3202 5.0 5.1 SERIAL COMMUNICATIONS Overview Communication with the MCP3202 is done using a standard SPI-compatible serial interface. Initiating communication with the device is done by bringing the CS line low. See Figure 5-1. If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and DIN high will constitute a start bit. The SGL/DIFF bit and the ODD/SIGN bit follow the start bit and are used to select the input channel configuration. The SGL/DIFF is used to select single ended or psuedo-differential mode. The ODD/SIGN bit selects which channel is used in single ended mode, and is used to determine polarity in pseudo-differential mode. Following the ODD/SIGN bit, the MSBF bit is transmitted to and is used to enable the LSB first format for the device. If the MSBF bit is high, then the data will come from the device in MSB first format and any further clocks with CS low will cause the device to output zeros. If the MSBF bit is low, then the device will output the converted word LSB first after the word has been transmitted in the MSB first format. See Figure 5-2. Table 5-1 shows the configuration bits for the MCP3202. The device will begin to sample the analog input on the second rising edge of the clock, after the start bit has been received. The sample period will end on the falling edge of the third clock following the start bit. On the falling edge of the clock for the MSBF bit, the device will output a low null bit. The next sequential 12 clocks will output the result of the conversion with MSB first as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 12 data bits have been transmitted and the device continues to receive clocks while the CS is held low, (and MSBF = 1), the device will output the conversion result LSB first as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 6.1 for more details on using the MCP3202 devices with hardware SPI ports. Config Bits Sgl/ Diff Single Ended Mode PseudoDifferentiaL Mode TABLE 5-1: 1 1 0 0 Odd/ sign 0 1 0 1 Channel Selection GND 0 + -- IN+ IN1 -- + ININ+ - Configuration Bits for the MCP3202. tCYC tCSH CS tSUCS CLK tCYC DIN Start SGL/ ODD/ MS DIFF SIGN BF Don't Care Start SGL/ ODD/ DIFF SIGN DOUT HI-Z tSAMPLE Null Bit B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* tCONV tDATA** HI-Z * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. See Figure 5-2 below for details on obtaining LSB first data. ** tDATA: during this time, the bias current and the comparator power down while the reference input becomes a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros. FIGURE 5-1: Communication with the MCP3202 using MSB first format only. (c) 2006 Microchip Technology Inc. DS21034D-page 13 MCP3202 tCYC CS tSUCS CLK Power Down tCSH DIN SGL/ DIFF ODD/ SIGN MSBF Start Don't Care DOUT HI-Z tSAMPLE Null B11 B10 B9 Bit B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 *B10 B11 HI-Z (MSB) tCONV tDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. ** tDATA: During this time, the bias circuit and the comparator power down while the reference input becomes a high impedance node, leaving the CLK running to clock out LSB first data or zeroes. FIGURE 5-2: Communication with MCP3202 using LSB first format. DS21034D-page 14 (c) 2006 Microchip Technology Inc. MCP3202 6.0 6.1 APPLICATIONS INFORMATION Using the MCP3202 with Microcontroller (MCU) SPI Ports in the `low' state, while Figure 6-2 shows the similar case of SPI Mode 1,1 where the clock idles in the `high' state. As shown in Figure 6-1, the first byte transmitted to the A/D Converter contains seven leading zeros before the start bit. Arranging the leading zeros this way produces the output 12 bits to fall in positions easily manipulated by the MCU. The MSB is clocked out of the A/D Converter on the falling edge of clock number 12. After the second eight clocks have been sent to the device, the MCU receive buffer will contain three unknown bits (the output is at high impedance until the null bit is clocked out), the null bit and the highest order four bits of the conversion. After the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Easier manipulation of the converted data can be obtained by using this method. With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the rising edge. Depending on how communication routines are used, it is very possible that the number of clocks required for communication will not be a multiple of eight. Therefore, it may be necessary for the MCU to send more clocks than are actually required. This is usually done by sending `leading zeros' before the start bit, which are ignored by the device. As an example, Figure 6-1 and Figure 6-2 show how the MCP3202 can be interfaced to a MCU with a hardware SPI port. Figure 6-1 depicts the operation shown in SPI Mode 0,0, which requires that the SCLK from the MCU idles CS SCLK MCU latches data from A/D Converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Data is clocked out of A/D Converter on falling edges DIN HI-Z Start SGL/ DIFF MSBF ODD/ SIGN Don't Care DOUT MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock) NULL B11 BIT Start Bit B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X X X X X X X 1 SGL/ ODD/ MSBF DIFF SIGN X X X X X X X X X X X X X X X X X X X X X X X X 0 B11 (Null) B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X = Don't Care Bits Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits Data stored into MCU receive register after transmission of last 8 bits FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low). CS MCU latches data from A/D Converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCLK Data is clocked out of A/D Converter on falling edges DIN HI-Z Start MSBF ODD/ SIGN SGL/ DIFF Don't Care DOUT MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock) NULL B11 BIT Start Bit B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 1 SGL/ ODD/ MSBF DIFF SIGN X X X X X X X X X X X X X X X X X X X X X X X X 0 B11 (Null) B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data stored into MCU receive register after transmission of first 8 bits X = Don't Care Bits Data stored into MCU receive register after transmission of second 8 bits Data stored into MCU receive register after transmission of last 8 bits FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high). (c) 2006 Microchip Technology Inc. DS21034D-page 15 MCP3202 6.2 Maintaining Minimum Clock Speed 6.4 Layout Considerations When the MCP3202 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample cap while the conversion is taking place. At 85C (worst case condition), the part will maintain proper charge on the sample capacitor for at least 1.2 ms after the sample period has ended. This means that the time between the end of the sample period and the time that all 12 data bits have been clocked out must not exceed 1.2 ms (effective clock frequency of 10 kHz). Failure to meet this criteria may induce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire conversion cycle, the A/D Converter does not require a constant clock speed or duty cycle, as long as all timing specifications are met. When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 0.1 F is recommended. Digital and analog traces should be separated as much as possible on the board and no traces should run underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a "star" configuration can also reduce noise by eliminating current return paths and associated errors. See Figure 6-4. For more information on layout tips when using A/D Converters, refer to AN688 "Layout Tips for 12-Bit A/D Converter Applications" (DS00688). VDD Connection 6.3 Buffering/Filtering the Analog Inputs If the signal source for the A/D Converter is not a low impedance source, it will have to be buffered or inaccurate conversion results may occur. It is also recommended that a filter be used to eliminate any signals that may be aliased back into the conversion results. This is illustrated in Figure 6-3 below where an op amp is used to drive the analog input of the MCP3202. This amplifier provides a low impedance output for the converter input and a low pass filter, which eliminates unwanted high frequency noise. Low pass (anti-aliasing) filters can be designed using Microchip's interactive FilterLabTM software. FilterLab will calculate capacitor and resistor values, as well as, determine the number of poles that are required for the application. For more information on filtering signals, see the application note AN699 "Anti-Aliasing Analog Filters for Data Acquisition Systems. " Device 4 Device 1 Device 3 Device 2 VDD 10 F FIGURE 6-4: VDD traces arranged in a `Star' configuration in order to reduce errors caused by current return paths. R1 VIN C1 R2 C2 MCP601 + - 0.1 F IN+ MCP3202 IN- R3 R4 FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a 2nd order anti-aliasing filter for the signal being converted by the MCP3202. DS21034D-page 16 (c) 2006 Microchip Technology Inc. MCP3202 7.0 7.1 PACKAGING INFORMATION Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW Example: MCP3202 e3 I/PNNN YYWW 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Example: MCP3202 e3 ISNYYWW NNN 8-Lead MSOP Example: XXXXXX YWWNNN 3202I e3 YWWNNN 8-Lead TSSOP Example: XXXX YYWW NNN 3202 IYWW NNN Legend: XX...X Y YY WW NNN e3 * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( 3 ) e can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. (c) 2006 Microchip Technology Inc. DS21034D-page 17 MCP3202 8-Lead Plastic Dual In-line (P) - 300 mil Body (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 E A A2 c L A1 eB B1 p B MAX Number of Pins Pitch Top to Seating Plane A .140 .170 4.32 Molded Package Thickness A2 .115 .145 3.68 Base to Seating Plane .015 A1 Shoulder to Shoulder Width E .300 .313 .325 8.26 Molded Package Width E1 .240 .250 .260 6.60 Overall Length D .360 .373 .385 9.78 Tip to Seating Plane L .125 .130 .135 3.43 c Lead Thickness .008 .012 .015 0.38 Upper Lead Width B1 .045 .058 .070 1.78 Lower Lead Width B .014 .018 .022 0.56 Overall Row Spacing eB .310 .370 .430 10.92 Mold Draft Angle Top 5 10 15 15 Mold Draft Angle Bottom 5 10 15 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 Units Dimension Limits n p MIN INCHES* NOM 8 .100 .155 .130 MAX MIN MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 DS21034D-page 18 (c) 2006 Microchip Technology Inc. MCP3202 8-Lead Plastic Small Outline (SN) - Narrow, 150 mil Body (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D 2 B n 1 h 45 c A A2 L A1 MAX Number of Pins Pitch Overall Height A .053 .069 1.75 Molded Package Thickness A2 .052 .061 1.55 Standoff A1 .004 .010 0.25 Overall Width E .228 .244 6.20 Molded Package Width E1 .146 .157 3.99 Overall Length D .189 .197 5.00 Chamfer Distance h .010 .020 0.51 Foot Length L .019 .030 0.76 Foot Angle 0 8 8 c Lead Thickness .008 .010 0.25 Lead Width B .013 .020 0.51 Mold Draft Angle Top 0 15 15 Mold Draft Angle Bottom 0 15 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 Units Dimension Limits n p MIN INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX MIN MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 (c) 2006 Microchip Technology Inc. DS21034D-page 19 MCP3202 8-Lead Plastic Micro Small Outline Package (MS) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 e b A2 c A A1 Units Dimension Limits N e A Thickness A2 A1 E Width E1 D L L1 c b L1 MILLIMETERS NOM 8 0.65 BSC -- 0.85 -- 4.90 BSC 3.00 BSC 3.00 BSC 0.60 0.95 REF -- -- -- L MIN MAX Number of Pins Pitch Overall Height Molded Package Standoff Overall Width Molded Package Overall Length Foot Length Footprint Foot Angle Lead Thickness Lead Width -- 0.75 0.00 1.10 0.95 0.15 0.40 0 0.08 0.22 0.80 8 0.23 0.40 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing No. C04-111, Sept. 8, 2006 DS21034D-page 20 (c) 2006 Microchip Technology Inc. MCP3202 8-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body (TSSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 e D 2 1 n b c L A1 A2 A Units Dimension Limits Number of Pins n Pitch e Overall Height A Molded Package Thickness A2 Standoff A1 Overall Width E Molded Package Width E1 Molded Package Length D Foot Length L Foot Angle Lead Thickness c Lead Width b Mold Draft Angle Top Mold Draft Angle Bottom MIN - .031 .002 .169 .114 .018 0 .004 .007 INCHES NOM 8 .026 BSC - .039 - .252 BSC .173 .118 .024 - - - 12 REF 12 REF MAX MIN .047 .041 .006 .177 .122 .030 8 .008 .012 MILLIMETERS* NOM MAX 8 0.65 BSC - - 1.20 0.80 1.00 1.05 0.05 - 0.15 6.40 BSC 4.30 4.40 4.50 2.90 3.00 3.10 0.45 0.60 0.75 0 - 8 0.09 - 0.20 0.19 - 0.30 12 REF 12 REF *Controlling Parameter Notes: 1. Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M REF: Reference Dimension, usually without tolerance, for information purposes only. See ASME Y14.5M Drawing No. C04-086 Revised 7-25-06 (c) 2006 Microchip Technology Inc. DS21034D-page 21 MCP3202 NOTES: DS21034D-page 22 (c) 2006 Microchip Technology Inc. MCP3202 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Performance Grade X Temperature Range /XX Package Examples: a) b) Device: MCP3202: 12-Bit Serial A/d Converter MCP3202T: 12-Bit Serial A/D Converter (Tape and Reel) (SOIC, MSOP and TSSOP package only) MCP3202-I/MS: = Industrial temperature, MSOP package. MCP3202-BI/P: = B Performance grade, industrial temp., PDIP package MCP3202-CI/SN: = C Performance grade, industrial temp., SOIC package MCP3202T-BI/SN: = Tape and Reel, B Performance grade, industrial temp., SOIC package MCP3202T-CI/ST: = Tape and Reel, C Performance grade, industrial temp., TSSOP package. c) d) Performance Grade: B C = 1 LSB INL (TSSOP not available) = 2 LSB INL a) Temperature Range: I = -40C to +85C Package: MS P SN ST = = = = Plastic Micro Small Outline (MSOP), 8-Lead Plastic DIP (300 mil Body), 8-Lead Plastic SOIC (150 mil Body), 8-Lead TSSOP (4.4 mm Body), 8-Lead (C Grade only) (c) 2001 Microchip Technology Inc. DS21034C-page23 MCP3202 NOTES: DS21034C-page24 (c) 2001 Microchip Technology Inc. MCP3202 APPENDIX A: REVISION HISTORY Revision D (December 2006) This revision includes updates to the packaging diagrams. (c) 2006 Microchip Technology Inc. DS21034D-page 25 NOTES: DS21034D-page 26 (c) 2006 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PIC(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2006 Microchip Technology Inc. DS21034D-page 27 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256 ASIA/PACIFIC India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 10/19/06 DS21034D-page 28 (c) 2006 Microchip Technology Inc. |
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